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AR# 22662

LogiCORE XAUI v6.1 - Example design contains incorrect period value for DCLK in the calibration block


The value of the C_DCLK_PERIOD_NS for cal_block_v_1_2_1 does not match the clock period generated by the demo testbench in the example design provided with the XAUI v6.1 Core.


To work around this, set the period of DCLK (50 MHz in the example design) accordingly in the "<xaui_component_name>_top.v(hd)" file. To do this, find C_DCLK_PERIOD_NS and change the attribute from 50 to 20. If the period of DCLK is different from the example design value of 50 MHz, refer to the Calibration Block Documentation and modify the Calibration Block attributes as required.

AR# 22662
Date 05/19/2014
Status Archive
Type General Article
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