We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22665

LogiCORE Fibre Channel Arbitrated Loop v1.1 Core - Memory collisions occur during speed switch in demonstration testbench


Occasionally, when simulating the Fibre Channel Arbitrated Loop v1.1 Core with the demonstration testbench, a memory collision error occurs in the example design FIFO when the testbench switches from the higher speed to the lower speed.


These memory collision errors can be safely ignored.

AR# 22665
Date 05/19/2014
Status Archive
Type General Article
Page Bookmarked