# AR# 22675

## Description

When I attempt to generate a MAC FIR, the following error occurs:

"Error:sim:57"

This error occurs when the ratio of clock frequency to sample frequency results in a large number of cycles being available for the core to carry out the filtering operation. The core will try to create a filter that uses all the available cycles, resulting in a filter that is too large for the core to support.

This occurs under the following conditions:

Single Rate:

- ceil( num coefficients / floor( (clock freq/sample freq)/channels)) * floor( (clock freq/sample freq)/channels) > 1039

- If symmetry is applied, then num coefficients is replaced with ceil(num coefficients / 2).

Interpolation:

- ceil( num coefficients / floor( (clock freq/sample freq)/(channels*rate)) ) * rate * floor( (clock freq/sample freq)/channels) > 1039

Decimation:

- ceil(ceil( num coefficients/rate) / floor( (clock freq/sample freq)/channels) ) * rate * floor( (clock freq/sample freq)/channels) > 1039

Half-band Single Rate:

- ceil( (ceil( num coefficients/2)/2) / floor( (clock freq/sample freq)/channels) ) * 2 * floor( (clock freq/sample freq)/channels) > 1039

Half-band Decimation:

ceil( (ceil( num coefficients/2)/2) / ( floor( (clock freq/sample freq)/channels)*2 ) ) * 2 * floor( (clock freq/sample freq)/channels) > 1039

Half-band Interpolation:

- ceil( (ceil( num coefficients/2)/2) / floor( (clock freq/sample freq)/channels) ) * 2 * floor( (clock freq/sample freq)/channels) > 1039

## Solution

To work around this issue, specify a smaller ratio between clock frequency and sample frequency by reducing the clock frequency or increasing the sample frequency. The most common occurrence of this error would be in a single MAC implementation where the filter could be implemented using a lower clock frequency than is specified.

In this case, the required clock frequency will be the sample frequency times the number of channels times the number of coefficients divided by the rate (for interpolation cases only). The ND control signal should then be used to operate the filter at the desired rate while using the original higher clock frequency. The core will sit idle after finishing filter calculations on the current sample before the next input sample is received and processed.

This will be addressed in v2.0 of the FIR Compiler.

AR# 22675
Date 12/15/2012
Status Active
Type General Article