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AR# 22719

PCI Express v3.1 - Why are TRN_RREM and TRN_TREM ports being placed on the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep cores?


When using CORE Generator 8.1i IP1I release to generate a PCI Express v3.1 pci_exp_1_lane_32b_ep or pci_exp_1_lane_64b_ep core, the core has a top-level output port called TRN_RREM and top-level input port called TRN_TREM. Is this right?


This issue has been fixed in the current release. Please see (Xilinx Answer 22320) for more details.

AR# 22719
Date 05/19/2014
Status Archive
Type General Article
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