The PCI Express core implements one PCI Express Extended Capability. This is the Serial Number Register as defined in section 7.12.2 of the PCI Express Specification v1.1. Reads to this register, or any user PCI Express Extended Capability register (0x400 to 0xFFF), seem to be returning the Device and Vendor ID or all 0s when using the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep cores.
This issue has been fixed in the current release.
For more details on the v3.1 PCI Express core, see (Xilinx Answer 22320).
For more details on the v1.3 PCI Express PIPE core, see (Xilinx Answer 22322).