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AR# 22737

8.1i Virtex-4 PAR - "ERROR:Place:629 on DSP48 slices that should have common signals on their control pins."


I have instantiated DSP48 slices in my design, and constrained them to be located in the same tile since I know they share all signals with shared routing resources. When I try to implement the design, the following error occurs:

"ERROR:Place:629 - DSP components MY_DSP_1 and MY_DSP_2 are locked together in a single DSP tile, however they do not share common control signals on their RSTC, CEC pins. The resulting placement will therefore be unroutable."

Since I instantiated these signals, I know that they should be shared. Why am I getting this error?


Synthesis only allows a certain number of loads on a net. If the RST or CE nets drive more than that number of signals, the signal may have been buffered. In XST, you can increase the MAX FANOUT option in synthesis for the design as a whole, or set a MAX_FANOUT constraint on that specific net (as described in the XST User Guide).

AR# 22737
Date 12/15/2012
Status Active
Type General Article