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FPGA Express - Error: Undefined macro `ifdef at or near token '`ifdef', VE-0
Keywords: Foundation Express, FPGA Express, Verilog, VE-0, `ifdef
If a Verilog design uses the `ifdef compiler directive, the following error will occur during
the Analyze phase:
Error: Undefined macro `ifdef at or near token "`ifdef"
(File: C:\myproj\test\ifdef.v Line: 8) (VE-0)
The `ifdef directive is not supported by versions of FPGA Express up to and including 3.1.
This issue has been addressed in FPGA Express 3.2. See (Xilinx Solution 5791) for details.
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