When simulating with NC-Verilog, what does the following error mean?
"ncelab: *F,CUMSTS: Timescale directive missing on one or more modules."
The `timescale can be declared in any file.
The UNISIMS has 100ps / 10ps.
The SIMPRIMS has 1ps / 1ps.
The glbl.v has 100ps / 10ps.
The smallest precision of all the timescale directives determines the time unit of the simulation. For example:
`timescale 1 ns / 10 ps
`timescale 100 ns / 1 ns
`timescale 1 ps / 100 fs
The first timescale indicates that the time units for module1 are in multiples of 1 ns and it is precise to 10 ps. Thus, the smallest timestep for the simulator is 10 ps.
The second timescale is 100 ns / 1 ns. Because 1 ns is greater than 10 ps, the smallest timestep remains 10 ps.
The third timescale is 1 ps / 100 fs. Because 100 fs is smaller than 10 ps, the smallest simulator timestep now becomes 100 fs.
The `timescale compiler directive is optional. Designs that do not contain this require no modification, and the default of 1 ns / 1 ns is used. However, if the design includes a `timescale compiler directive for any module definition, then all other modules' definitions require this as well. Otherwise, NC-Verilog flags this as an error.
The -timescale option can be issued to ncelab rather than adding the `timescale directive to all the modules.