For Virtex-4 design implementations the use of the IDELAY in the DDR2 IOB modules is required. When using any IDELAY component within the FPGA, an IDELAYCTRL module is necessary. The IDELAYCTRL module provides the necessary tap increments for each IDELAY module to which it is associated.
In the ISE tools, if only one IDELAYCTRL module is instantiated and the DDR2 signal pin assignments are across multiple clock regions, the tools will replicate the IDELAYCTRL module. To prevent the tools from duplicating the IDELAYCTRL to all locations on the FPGA, the user must specify how many IDELAYCTRL modules are needed. This is specified with the C_NUM_IDELAYCTRL design parameter. It is the responsibility of the designer to constrain each IDELAYCTRL location based on the clock regions where DDR2 IOB signals reside.
For instance, if C_NUM_IDELAYCTRL = 4, then the user must add UCF constraints to location constrain these modules, as shown on Figure 37
Figure 37: Virtex-4 IDELAY Constraints
INST plb_ddr2_0/*/IDELAYCTRL_I0 LOC=IDELAYCTRL_XnYm;
INST plb_ddr2_0/*/IDELAYCTRL_I1 LOC=IDELAYCTRL_XnYm;
INST plb_ddr2_0/*/IDELAYCTRL_I2 LOC=IDELAYCTRL_XnYm;
INST plb_ddr2_0/*/IDELAYCTRL_I3 LOC=IDELAYCTRL_XnYm;