After upgrading to 8.1i sp1, PAR now fails to route my design, with the following error message. It worked very well in previous revisions. What is causing this routing failure?
"ERROR:Route:424 -This design is unroutable. To evaluate the problem please use fpga_editor.
Conflict 1, detected on wire:DUMMY(-54384,-23455)
Net:CLK on pin OTCLK1 on location PAD224 has a routing conflict with
Net:CLK200 on pin OTCLK1 on location PAD223"
NOTE: This Answer Record is a good match for your problem only if the pin name involved is OTCLK1, OTCLK2, ICLK1, or ICLK2.
This routing problem is caused by PAR failing to correctly BEL swap IOB FFs so that two FFs with different clocks do not conflict for the clock routing resource shared by IOB pairs. See (Xilinx Answer 11747) for more details regarding the shared resources.
This problem will be fixed in version 8.1i sp3. Meanwhile, to work around this issue, use a mapping BEL constraint on the offending FF to resolve the routing conflict, using the following steps:
1. Load the partially routed design output by PAR into FPGA Editor and examine the problem IOB pair by searching for the wire name mentioned in the error message "Find Wire DUMMY(-54384,-23455)".
2. It can be helpful to turn on the Local Line and/or Pin Wire layers to easily identify the IOB pairings.
3. Examine the contents of each IOB in the pair using Logic Block Editor.
4. Identify a FF (TFF1, TFF2, OFF1, OFF2, IFF1 or IFF2) that can be moved to resolve the conflict.
5. Select the FF BEL in the Logic Block Editor to identify the BEL name in the history window:
<OFF1>; bel <USER_APP/video/video/Tags>
6. For this example a BEL named "USER_APP/video/video/Tags" is incorrectly packed into the OFF1 BEL. The problem can be resolved with the following UCF constraint forcing MAP to pack the BEL in OFF2 which used a different clock resource:
INST "USER_APP/video/video/Tags" BEL = OFF2 ;
7. Rerun the flow from NGDBUILD, or rerun Implementation in ISE.