Reference #: 17927
General Description:
Timing analysis on constraints associated with the special
pads MD0, MD1, MD2 may give the following result:
<OUTPUT>
Path $I1 to QOUT contains 1 level of logic:
Path starting from Comp: MD0.I (from $Net00005_)
To Delay type Delay(ns) Physical
Resource
------------------------------------------------- --------
CLB_R10C1.C2 net 0.946R $Net00002_
Tdick 1.000R QOUT
QOUT
-------------------------------------------------
Total (51.4% logic, 48.6% route) 1.946ns
--------------------------------------------------------------
==============================================================
Timing constraint: TS02 = MAXDELAY FROM TIMEGRP "FFS(QOUT)" TO
TIMEGRP "PADS(DOUT)" 20 nS ;
0 items analyzed, 0 timing errors detected.
</OUTPUT>
In this example, DIN is assigned to MD0, and DOUT is assigned
to MD1. While MD0 is recognized as a CLB, MD1 is not even
seen by TRCE.
The current M1.3 does not process timing constraints
attached to MD0, MD1, or MD2. The same problem exists in XACTstep 5.2.1/6.0.1.
AR# 2279 | |
---|---|
Date | 01/18/2010 |
Status | Archive |
Type | General Article |