For OPB Burst Reads of a PCI target, when the "Inhibit OPB Master Read Transfers" bit is set under "Inhibit Transfers" on the error register, the bridge does not issue OPB timeouts as described in the Product Specification for PCI transactions with abnormal terminations. Instead, retries are issued. When this bit is clear, the OPB timeout occurs as expected.
NOTE: For OPB Burst Writes to a PCI target while the "Inhibit OPB Master Write Transfers" bit is set, the bridge acts as expected.
The product specification has been updated to properly describe the bridge operation with the new IPIF v2.00.j module located in the latest EDK 8.1i Service Pack, available at:
The first service pack containing the fix is EDK 8.1i Service Pack 1.