We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22909

EDK 7.1, 8.1 - XAPP901/UG096 reference design, after being downloaded, does not execute or is unreliable. Set C_DFS_FREQUENCY_MODE to 'HIGH'


After I downloaded the XAPP901/UG096 reference design to the development board, it would not execute or was unreliable.


This solution is applicable for both EDK 7.1 and EDK 8.1. 


The reference design uses a 300 MHz output (CLKFX) from dcm_0 to clock the PowerPC. The C_DFS_FREQUENCY_MODE parameter of that DCM (dcm_0) should be set to HIGH. This is not done automatically by Base System Builder. The change can be done via Platform Studio in the add/edit cores dialog box or in the MHS file directly. 


This change is needed for the reference design to work reliably. 


Please refer to (Xilinx Answer 21936) for additional information.

AR# 22909
Date 05/20/2014
Status Archive
Type General Article
Page Bookmarked