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AR# 22919

10.1 PACE - DRC results in errors related to my local clock pins in a Virtex-4, even though they are locked to valid Clock Capable I/O locations


In a Virtex-4 design using clock capable I/O driving a BUFIO and correctly locked to a clock capable I/O, PACE results in the following error in DRC:

"I/O is using a clock buffer but is not placed in a GCLK or GCK type pin. Please move it to a GCLK or GCK pin."

However, my design implements without further errors.


As long as you are confident that the clock is correctly locked to a clock-capable I/O and only driving a BUFIO, you can ignore this error. Check your pin location in the Virtex-4 Packaging and Pinout Specification in the Virtex-4 User Guide:


You can check that the routing from the clock-capable I/O to the BUFIO is correct in FPGA Editor.

This problem has been fixed in the latest 9.1i Service Pack available at:


The first service pack containing the fix is 9.1i Service Pack 2.

AR# 22919
Date 12/15/2012
Status Active
Type General Article
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