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AR# 22924

LogiCORE PCI v3.155, 8.1isp2, Virtex-4 - PAR fails to place logic within three adjacent clock regions, causing unrouted clock nets

Description

PAR fails to place logic within three adjacent clock regions, causing unrouted clock nets. The following warning is issued:

"WARNING:Route:436 - The router has detected an unroutable situation for one or more connections."

PCI 66 MHz designs for Virtex-4 devices require the use of the regional clock inputs. All logic clocked by this clock must fall within three adjacent clock boundaries.

Please see the Virtex-4 User Guide for more information about regional clock usage. Designs that were working in ISE 8.1i may fail in 8.1iSP2 because PAR is not placing all logic being clocked by the PCI input clock into three adjacent regions.

Solution

To work around this issue, area group constraints must be placed on the logic to force PAR to place the logic clocked by the PCI clock into three adjacent clock regions. The following examples use AREA_GROUP constraints to achieve this.

Note that these examples are for the UCF files that are provided with the core delivered by CORE Generator. For UCF files generated by the PCI UCF Generator or for other placements, you must create valid constraints that will allow the logic to be placed correctly.

For 32-bit designs using the 4vfx20ff672_32_33r.ucf or 4vfx20ff672_32_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X36Y64:SLICE_X59Y127 ;

For 64-bit designs using the 4vfx20ff672_64_33r.ucf or 4vfx20ff672_64_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X36Y32:SLICE_X59Y127 ;

For 32-bit designs using the 4vlx25ff668_32_33r.ucf or 4vlx25ff668_32_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X28Y128:SLICE_X55Y191 ;

For 64-bit designs using the 4vlx25ff668_64_33r.ucf or v4lx25ff668_64_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X28Y96:SLICE_X55Y191 ;

For 32-bit designs using the 4vsx35ff668_32_33r.ucf or 4vsx35ff668_32_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X40Y128:SLICE_X79Y191 ;

For 64-bit designs using the 4vsx35ff668_64_33r.ucf or 4vsx35ff668_64_66r.ucf:

INST "*" AREA_GROUP = "AG_FIX" ;

AREA_GROUP "AG_FIX" RANGE = SLICE_X40Y96:SLICE_X79Y191 ;

A PING Design results in an unrouted clock net after the above constraints are applied

Three ports on the PING example design that comes with the core are not explicitly locked to pins in the provided UCF files. These are PING_DONE, PING_REQUEST32, and PING_REQUEST64. PAR must place these three pins onto valid IOBs in the three adjacent clock regions. PAR in 8.1iSP2 will not always do this correctly.

To work around this issue, add three LOC constraints to the UCF file being used to place these pins on valid sites. An example for the 4vlx25ff668_64_33r.ucf or v4lx25ff668_64_66r.ucf is the following:

NET "PING_DONE" LOC ="D10" ;

NET "PING_REQUEST32" LOC = "C10" ;

NET "PING_REQUEST64" LOC ="D9" ;

AR# 22924
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article