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AR# 22958

LogiCORE PCI Express - What is the Swap A-B Pairs option? How do I change the MGT coordinates for a given lane?

Description

When I generate a PCI Express core through CORE Generator, one of the options is "Swap A-B Pairs." What does this option do?

Solution

"Swap A-B Pairs" allows users to swap the lane numbers that coincide with a particular MGT tile. In Virtex-4 devices, MGTs are arranged in pairs of tiles. One tile is the "A" tile and one is the "B" tile. The PCI Express core associates one lane per tile.

If "Swap A-B Pairs" is unchecked or marked "0":

- A transceivers have lanes 0, 2, 4, 6

- B transceivers have lanes 1, 3, 5, 7

If "Swap A-B Pairs" is checked or marked "1":

- A transceivers have lanes 1, 3, 5, 7

- B transceivers have lanes 0, 2, 4, 6

By default, the UCF generated through CORE Generator for the pci_exp_8_lane_64b_ep, pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep core always assumes "Swap A-B Pairs" is set to "0" or is unchecked (i.e., this option in CORE Generator has no impact on the generated UCF file).

If you are using the pci_exp_1_lane_64b_ep or pci_exp_4_lane_64b_ep, these cores are not yet supported in CORE Generator and are delivered through a zip file from the PCI Express lounge. This core has a 1024-bit configuration vector input to the core. The "Swap A-B Pairs" option is set through Bit 509.

You have the option of swapping the lanes in a given MGT pair. Valid lane ordering would either be 0, 1, 2, 3, 4, 5, 6, 7 or 1, 0, 3, 2, 5, 4, 7, 6. This can be with Lane 0 or 1 on the top edge or bottom edge of the device. However, other orderings are not valid. Although this example is given for x8, it applies to the x1 and x4 also. (Note that in an x1 core, even though there is only one PCI Express lane, both MGT tiles are used. One is used for the actual lane and the other is reserved but still instantiated inside the core.)

For a given MGT tile, GT11_XnYeven is associated with MGT B and GT11_XnYeven+1 is associated with MGT A. This means the B transceivers are on the even Y coordinate and the A transceivers are on the odd Y coordinate. Please see the Virtex-4 RocketIO MGT User Guide for more information on this:

http://www.xilinx.com/support/mysupport.htm#Virtex-4

x1 Example

The following is an example of the default MGT placement location for a x1 32-bit core on an FX60-FF1152 device as produced by CORE Generator:

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" LOC = "GT11_X1Y7" ; # COL 1

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" LOC = "GT11_X1Y6" ; # COL 1

NOTE: The paths may vary depending upon the name selected for your core.

If you want to swap the tiles, check the "Swap A-B Pairs" box in CORE Generator. In the UCF, change the coordinates associated with the PCI Express lanes. You must also add the GT11_MODE constraints as follows:

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" LOC = "GT11_X1Y6" ; # COL 1

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" LOC = "GT11_X1Y7" ; # COL 1

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST" GT11_MODE = B;

INST "ep/BU2/U0/pci_exp_1_lane_32b_ep0/plm/v4f_mgt/gt11_by1/GT11_PCIEXP_2_INST2" GT11_MODE = A;

Without the GT11_MODE constraints, PAR will not place the MGTs correctly.

Remember that if you are using the pci_exp_1_lane_64b_ep or pci_exp_4_lane_64b_ep, these cores are not yet supported in CORE Generator and are delivered through a zip file from the PCI Express lounge. This core has a 1024-bit configuration vector input to the core. The "Swap A-B Pairs" option is set through Bit 509. Set this to "1" to swap the default pairing.

x4 Example

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" LOC = "GT11_X1Y7" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" LOC = "GT11_X1Y6" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST3" LOC = "GT11_X1Y5" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST4" LOC = "GT11_X1Y4" ; # COL 1

NOTE: The paths may vary, depending on the name selected for your core.

If you want to swap the tiles, check the "Swap A-B Pairs" box in CORE Generator. In the UCF, change the coordinates associated with the PCI Express lanes. You must also add the GT11_MODE constraints as follows:

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" LOC = "GT11_X1Y6" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" LOC = "GT11_X1Y7" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST3" LOC = "GT11_X1Y4" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST4" LOC = "GT11_X1Y5" ; # COL 1

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" LOC GT11_MODE = B;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" LOC GT11_MODE = A;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST3" LOC GT11_MODE = B;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST4" LOC GT11_MODE = A;

Without the GT11_MODE constraints, PAR will not place the MGTs correctly.

Remember that if you are using the pci_exp_1_lane_64b_ep or pci_exp_4_lane_64b_ep, these cores are not yet supported in CORE Generator and are delivered through a zip file from the PCI Express lounge. This core has a 1024-bit configuration vector input to the core. The "Swap A-B Pairs" option is set through Bit 509. Set this to "1" to swap the default pairing.

The above examples are applicable for different devices and for the x8 core.

Device MGT Location and "Swap A-B Pair" Settings Example

The two tables below illustrate possible combinations of placements and "Swap A-B Pair" settings for the XC4VFX60-FF1152. This information can be created for any FX device using the information in the Virtex-4 RocketIO MGT User Guide: http://www.xilinx.com/support/mysupport.htm#Virtex-4.This document contains similar information for other devices.

Using the MGT location coordinate and pin information found in the RocketIO MGT User Guide, apply the "Swap A-B Pair" option and choose your PCI Express lane locations. Two tables illustrate either top-up lane ordering or bottom-down lane ordering. The specific ordering is chosen depending upon the board layout characteristics. Note that the core currently supports placement only on the Column 1 MGTs as shown in these tables.

XC4VFX60-FF1152 Placement Option 1
XC4VFX60-FF1152 Placement Option 1

XC4VFX60-FF1152 Placement Option 2
XC4VFX60-FF1152 Placement Option 2

Note that for x1 or x4 cores, you can base your placement on these tables as well.

AR# 22958
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article