We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22968

8.1 AccelDSP Synthesis Tool - What is the maximum data bit width (word size) supported?


What is the maximum data bit width (word size) supported?


The AccelDSP Synthesis Tool supports operations that require more than 53 bits (e.g., the multiplication between two 53 bits numbers), but reduces the result to 53 bits. Unsigned ports are limited to 31 bits, and signed ports are limited to 32 bits due to Verilog and VHDL language limitations. Unsigned ports have the 31 bit limitation because of the conversion to integer type in the RTL testbench. 


In 8.1, AccelWare IP that is auto-inferred by IP-Explorer has a maximum port width of 47 bits.

AR# 22968
Date 05/20/2014
Status Archive
Type General Article
Page Bookmarked