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AR# 22978

8.1 AccelDSP Synthesis Tool - How do I solve Verify -rtl failures?


How do I solve Verify -rtl failures?


The following are two common causes of Verify -rtl failures: 


- The RTL simulator stops (fatal error) because of a problem found in the RTL code. The solution is to examine the RTL code and, if necessary, compare it with the MATLAB. For example, suppose that you receive the following fatal error during Verify -rtl: 


 # ** Fatal: (vsim-3421) Value 2 is out of range 0 to 1. 

 # Time: 600 ns Iteration: 2 Process: /testbench/dut/ranger_process_clocked File: ../ranger.vhd 

 # Fatal error at ../ranger.vhd line 77 


 # Stopped at ../ranger.vhd line 77  

 # Stopped at ../ranger.vhd line 77  



In this case, the problem is that the RTL simulation ran a little longer than MATLAB and, as a result, encountered an array index exceeding its maximum value. The solution is to identify the vector in question from the RTL code or run MATLAB longer to help reproduce the problem during Verify -floatingpoint.  


- If the simulation results disagree between fixed point model and the RTL model, this might be caused by the following: 

* If you changed the MATLAB source but skipped the Verify -fixed point step. The solution is to re-run the Verify -fixedpoint through Verify -rtl steps. 

* Incorrect RTL generated by AccelDSP. Contact Customer Service if you think this might be the case. Some of the techniques to help narrow the issue are as follows: 

-- Identify the ports that have a mismatch. Add new ports for intermediate values before the problematic port is set, which will then be compared. In this way, you can isolate the line where the problem occurred. 

-- Enable the Fi Objects project option (in the Output section). This can solve the problem if the W-QTZ-0405 warning is displayed during Generate -fixedpoint.

AR# 22978
Date 05/20/2014
Status Archive
Type General Article