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AR# 23031

LogiCORE SPI-4.2 (POS-PHY L4) v6.3 - "ERROR:Place:686 - Clock placer is unable to partition the design so that all the clock region constraints are honored."

Description

When implementing the SPI-4.2 design, you get following Par error: 

 

ERROR:Place:686 -  

Clock placer is unable to partition the design so that all the clock region constraints are honored. The RPM 

pl4_src_top1/pl4_src_io0/srcreset_cp(0) is taller than a single clock region or wider than a single clock region. The 

clock placer handles all tall and wide RPMs (more than a region) in a special manner however the clock placer was not 

able to find a feasible solution. Locking this RPM by adding a RLOC_ORIGIN to this RPM may assist the clock placer in 

finding the solution. 

ERROR:Place:686 -  

Clock placer is unable to partition the design so that all the clock region constraints are honored. The RPM 

pl4_src_top1/pl4_src_io0/srcreset_cp(0) is taller than a single clock region or wider than a single clock region. The 

clock placer handles all tall and wide RPMs (more than a region) in a special manner however the clock placer was not 

able to find a feasible solution. Locking this RPM by adding a RLOC_ORIGIN to this RPM may assist the clock placer in 

finding the solution. 

ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the Global clocking required for this 

design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may 

be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that 

only one clock output signal for any Primary / Secondary pair of clocks may enter any region. For further 

information see the "Using Global Clock Networks" section in the V-II User Guide (Chapter 2: Design Considerations) 

Phase 4.30 (Checksum:26259fc) REAL time: 1 mins 19 secs

Solution

This error will occur when implenting SPI-4.2 core nd example design with following configuration: 

- targeting:2vp70FF1704 

- dynamic alignment 

- core i/o placed on banks 2 and 3 

- 128-bit user interface 

 

The workaround is to move tdclk0 BUFG from 4P to 3S. 

Open your UCF file and change following line: 

 

INST "pl4_src_top1/pl4_src_clk0/DCMbypassed.tdclk0_bufg0" LOC = BUFGMUX4P; 

(change "4P" to "3S") 

INST "pl4_src_top1/pl4_src_clk0/DCMbypassed.tdclk0_bufg0" LOC = BUFGMUX3S;

AR# 23031
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article