UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23032

8.1i HDL Language - How do I use the Verilog Replication operator {{ }} correctly?

Description

When using the code below, I do not obtain my expected output; I do not see the expected value in b. 

 

Example that does not work: 

================ 

module testcase(clk, reset, a, b); 

input wire clk; 

input wire reset; 

input wire [3:0] a; 

output reg [10:0] b; 

 

always @( posedge clk or negedge reset) 

begin 

if (~reset) 

b <= 10'h000 ; 

else 

b <= {a, {6{1}} } ; // line to change 

 

end 

endmodule 

================

Solution

This code does not work as the tool by default codes the value 1 on 32 bits so the value of a is ignored in {a, {6{1}} }.  

 

To work-around this issue, constraint the value on 1 as in the example {a, {6{1'b1}} } which could also have been written as {a, {3{2'b11}} }. 

 

Please see below the work-around of the code above. 

 

Correct Example: 

=============================== 

module testcase(clk, reset, a, b); 

input wire clk; 

input wire reset; 

input wire [3:0] a; 

output reg [10:0] b; 

 

always @( posedge clk or negedge reset) 

begin 

if (~reset) 

b <= 10'h000 ; 

else 

b <= {a, {6{1'b1}} } ; // correct line 

 

end 

endmodule 

 

 

==============================

AR# 23032
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article