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AR# 23073

CORE Generator 8.1- Verilog structural models do not have black box attributes for XST. This results in the core being optimized out in synthesis.


My core is being optimized out during synthesis. I have the .xco file in my project but during synthesis I get warnings like this one for every port on my core:

"WARNING:Xst:1305 - Output <dout> is never assigned. Tied to value 000000."

After MAP, I can see that the core is not being used at all.


This is a known issue for several cores when using Verilog for simulation for IP which use structural simulation models as opposed to behavioral simulation models (XilinxCoreLib).

To resolve this you can add the following lines to the Verilog model which is output for the core.

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of test is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of test is "black_box"

where "test" is the name of the core. This should be added just before the "endmodule" statement.
AR# 23073
Date 10/13/2010
Status Archive
Type General Article