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AR# 23111

ChipScope - Can both of the ChipScope design flows be used at the same time?


Is it possible to support both ChipScope tool design flows (inserter and core generator) at the same time in the same design? This would be useful for using both an inserted ILA Core (gives access to signals at different hierarchy levels without having to modify the HDL code) and an instantiated VIO core, which cannot be inserted.


From 12.1 forward this can be achieved by using the ChipScope tool CORE Generator flow to instantiate an ICON and VIO, and insert an ILA core with the PlanAhead/ChipScope flow.

Below are the steps needed to add the ILA in the PlanAhead flow. If the user needs to have VIO control, then they will need to add a VIO and ICON core using the Core Generator flow in ISE software initially. See AR 15341 known issues for this.

1. Create a new PlanAhead project.
2. Select add EDIF or NGD netlist from the ISE project.
3. Add the Ngc file from ISE and also use the add directories to add the ipcore_dir folder from the ISE project as this contains the existing ChipScope Cores:

4. Select Netlist Design and this will open the netlist.
5. Select ?Set-up ChipScope? from either the project manager or the wizard icon:

6. Select ?Add Remove Nets? and add the required signals to be monitored. The finish dialog should show 0 cores have been removed and 1 core has been added:

7. You should see the ISE ChipScope Cores as well as the PlanAhead added ChipScope core:

For further details on the PlanAhead flow please see the PlanAhead Tutorials:

AR# 23111
Date 12/17/2010
Status Active
Type Known Issues
  • ChipScope Pro - 12.1
  • ChipScope Pro - 12.2
  • ChipScope Pro - 12.3
  • ChipScope Pro - 13.1
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