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AR# 23188

8.1i Virtex-4 Modular Design - "ERROR:LIT:249 - CASCADEINB pin of RAMB16" during MAP


I am using the Modular Design flow on my design and when I run MAP, I receive the following error.

"ERROR:LIT:249 - CASCADEINB pin of RAMB16 symbol

"memory_0/physical_group_ram_0/N10347/ram_0/BU103" can be sourced only from a

CASCADEOUTB of a different RAMB16. Also, the CASCADEOUTB pin on a RAMB16 can

source only a single CASCADEINB pin of a different RAMB16."

This RAM should not have anything connected to the CASCADEINB pin, and when I run the design in the normal flat design flow, the Error does not occur. How do I work around this issue?

NOTE: This solution is only a good fit for your issue if you are using the Modular Design flow.


This issue is scheduled to be fixed in a future release. To work around it in the current tools, set the environment variable XIL_MAP_SKIP_LOGICAL_DRC. This environment variable should only be set to work around this specific issue and should be removed when implementing other designs.

For instructions on setting environment variables, please reference (Xilinx Answer 11630)

AR# 23188
Date 12/15/2012
Status Archive
Type General Article
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