We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23191

10.1 Virtex-II/-II Pro Speeds File - What is the definition of Tito in the timing report?


In the Timing Report (.twr file), the timing specification Tito is included. What is the definition of this timing parameter?


Tito is the delay between BX, XQ of FFX inside a slice. 


For more details about Virtex-II/-II Pro slice structure, refer to the "General Slice Timing Model and Parameters" section in Chapter 2 of "Virtex-II Pro and Virtex-II Pro X FPGA User Guide" (UG012): 


AR# 23191
Date 05/20/2014
Status Archive
Type General Article
Page Bookmarked