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AR# 23210

8.2i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:<numbers>"

Description

Keywords: signal, initialize, synthesis, synthesize

While running synthesis on my design, the following fatal error occurs:

"FATAL_ERROR:Xst:Portability/export/Port_Main.h:<numbers>"

Xilinx is actively trying to provide better error messages to help you debug the issue. This Answer Record contains some of the solutions that have fixed the fatal error.

Solution

Below are some reasons why this error might occur, and the solutions that have fixed the error:

Case 1:
This issue can occur when there are a large number of muxes that constitute combinatorial loops (mux extraction cannot handle them properly).

This can be verified by examining the XST log file and looking for the following:

"WARNING:Xst:2170 - Unit RS_X16Y4_V1R3 : the following signal(s) form a combinatorial loop: X13Y3/XROUTING/XD/XO/Mmux_O_N2, X8Y3/Z, X8Y3/XROUTING/XD/XO/Mmux_O_N1, X15Y3/XROUTING/XD/XO/Mmux_O_N6, X15Y3/XROUTING/XD/XO/Mmux_O_N1, X13Y3/XROUTING/XD/XO/Mmux_O_N1, X13Y3/D, X8Y3/D, X15Y3_W8O."

You can work around this issue by setting the mux extraction option to "no." To learn more about this option, refer to the XST User Guide accessible at:
http://www.xilinx.com/support/software_manuals.htm

1. In the Software Manuals page, under Current Software Manuals, click the appropriate link (depending on the design tools).
2. In the next page, click the PDF Collection link.
3. In the next page, click the Bookmarks tab on the left. Under Software Manuals, select the XST User Guide near the bottom of the tree.

This issue is scheduled to be fixed in ISE 9.1i.

Case 2:
This issue can occur when you infer a Dual Port Distributed RAM and a Dual Port Block RAM, and instantiate these two components in the top level.

You can work around this problem by instantiating the Dual Port Distributed RAM first, and then instantiating the Dual Port Block RAM.

Xilinx is currently investigating this issue.

Case 3:
This issue can occur when you use incremental synthesis. You can work around the problem by disabling incremental synthesis using one of the following methods:

Method 1

-- attribute incremental_synthesis: string;
-- attribute incremental_synthesis of incremental : entity is "yes";

Method 2

attribute incremental_synthesis: string;
attribute incremental_synthesis of incremental : entity is "no";

Xilinx is currently investigating this issue.

Case 4:
This issue can occur when two signals are tied to ground in the top level. If you add ports to these signals, so they are not always tied to ground, the fatal error does not occur.

This issue is scheduled to be fixed in ISE 9.1i.

Case 5:
This error occurs on Windows only when an old XST directory is not cleaned up.

To work around this issue, clean up the project files. For information on cleaning up project files, refer to the ISE Help.

NOTE: If these solutions do not help you resolve the problem, open a WebCase with Xilinx Technical Support at:
http://www.xilinx.com/support/clearexpress/websupport.htm
AR# 23210
Date Created 09/04/2007
Last Updated 07/05/2006
Status Active
Type General Article