My design fails in PAR with an unrouted global clock net. I understand that there is a hardware limitation that only eight global clocks can be routed in each clock region. Is not the placer aware of that limitation? What can I do to correct this problem?
The Global Clock Placer does automatically area constrain all global clock domains to ensure that no more than eight clock domains need to be routed within any clock region. Unfortunately, in this case, the clock region needed to route to PPC and EMAC sites is being miscalculated. This miscalculation can lead to an unroutable global clock connection in that clock region if the placer assigns eight other clocks to it. The unrouted clock will not necessarily be a PPC or EMAC clock.
It is possible to avoid this problem by assigning clock region constraints to each clock domain as follows:
NET "clk1" TNM_NET = "TNM_clk1" ;
TIMEGRP "TNM_clk1" AREA_GROUP = "AG_clk1" ;
AREA_GROUP "AG_clk1" RANGE = CLOCKREGION_X1Y2,CLOCKREGION_X1Y3 ;
It can also be very useful to examine the clock region usage in FPGA Editor which now displays a clock region layer since 8.1i. Reportgen can also be used to generate a report of clock region usage:
reportgen -clock_regions design.ncd
which creates a file named "design.clk_rgn"
NOTE: This problem can also lead to false placer errors with correctly constrained designs.
This problem has been fixed for version 8.2i. Patches are also available for 8.1i sp1 and sp3. A WebCase should be opened to request this patch. Please specify the revision and platform support needed.