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AR# 23227

8.1i Virtex-II PAR - Automatic clock placement fails for RPMs that span three clock regions


A design with a very large RPM fails during automatic clock placement. The RPM is so large that it is not possible to place it without spanning three clock regions, and the clock placer is incapable of constraining the macro appropriately. 


"ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the Global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any Primary / Secondary pair of clocks may enter any region. For further information see the "Using Global Clock Networks" section in the V-II User Guide (Chapter 2: Design Considerations)."


There are no plans to fix this problem. Large RPMs that span three clock regions should be locked down with an RLOC_ORIGIN constraint.

AR# 23227
Date 05/20/2014
Status Archive
Type General Article
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