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AR# 23228

Spartan-3/-3E/-3A/-6 BUFGMUX - What is the setup time for the select or enable signal of BUFGMUX?


What is the setup time for the select pin (S) of the BUFGMUX?


The Spartan-3 FPGA Generation User Guide and the Spartan-6 FPGA Clocking User Guide both state the following (or something similar) in the BUFGMUX section:
"The select line can change at almost any time, independent of the clock states or transitions. The only exception is a short setup time prior to a Low-to-High transition on the selected clock input, which can result in an undefined runt pulse output."
The setup time of the select pin (S)is reported in each device's respective datasheet and by the Timing Analyzer or TRCE as Tgsi0 and Tgsi1. This value is reported as part of the data vs. clock path analysis (e.g., when an "OFFSET IN" constraint is applied).

Clock Path Delay: -1.035ns (Levels of Logic = 2)

Clock Uncertainty: 0.000ns

Data Path: Select_line to BUFGMUX_1

Delay type Delay(ns) Logical Resource(s)

---------------------------- -------------------

Tiopi 1.686 Select_line


net (fanout=1) 1.344 Select_line_IBUF

Tgsi0 0.522 Delay has no logical resource correlation.

---------------------------- ---------------------------

Total 3.552ns (2.208ns logic, 1.344ns route)

(62.2% logic, 37.8% route)

Clock Path: CLKIN_1 to BUFGMUX_1

Delay type Delay(ns) Logical Resource(s)

---------------------------- -------------------

Tiopi 1.349 CLKIN_1


net (fanout=1) 0.488 CLKIN_1_IBUFG

Tdcmino -3.463 DCM_1

net (fanout=2) 0.591 CLK0_1

---------------------------- ---------------------------

Total -1.035ns (-2.114ns logic, 1.079ns route)


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 23228
Date 02/06/2013
Status Active
Type General Article
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