AR# 23238

8.1i EDK Sp2 - wrpfifo_v2_00_a, Write Packet FIFO returns an Error Acknowledge when a PLB Master writes to its reset port

Description

In the Write and Read Packet FIFO V2_00_a, the FIFO's bus interface returns an Error Acknowledge when a PLB Master writes to the Soft Reset register address (of the FIFO register space). This Error Acknowledge causes a PLB bus error and ultimately a Machine Check interrupt to the PPC405.

Solution

This problem has been fixed in the latest EDK 8.1i Service Pack, available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 8.1i Service Pack 2.

AR# 23238
Date 05/20/2014
Status Archive
Type General Article