AR# 23249

8.2i XST - "ERROR:NgdBuild:752 - Line xx in '<design>.ucf': Could not find instance(s) 'inst_lut100' in the design" - errors can be seen for designs that passed correctly in ISE 8.1i


After upgrading from 8.1i to 8.2i, XST users who have UCF location constraints might encounter the following error:

"ERROR:NgdBuild:752 - Line xx in '<design>.ucf': Could not find instance(s) 'inst_lut100' in the design. To suppress

this error, specify the correct instance name or remove the constraint. The 'Allow Unmatched LOC Constraints'

ISE property can also be set ( -aul switch for command line users )."

What has changed, and how can I fix my design?


XST changed the naming conventions for the instances created by VHDL generate statements. The names changed for Verilog generate statements as well, but only for instantiations of hierarchy (naming for primitives and black boxes are unchanged). This was done for two reasons:

1. To improve the predictability of the generated names. If two or more generate statements were in the same VHDL entity, the names in the second generate statement and beyond would be impacted by the generate statements that preceded it. Order of these statements also had an influence.

2. To provide consistent names between VHDL and Verilog. The naming conventions for the two languages are now identical for all cases (except Incremental Synthesis; see below). They are in the format "loopname[index].instancename".

To see the new naming conventions, please refer to the "Instance Naming Conventions" section in the latest version of the XST User Guide at:

Users may revert to the naming conventions from version 8.1i and earlier by setting a command line option in XST:

-old_instance_names 1 ( Refer XST User Guide)
AR# 23249
Date 11/20/2010
Status Archive
Type General Article