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AR# 23253

8.2 System Generator for DSP - How can I improve the synthesis results of the clock wrapper clock enable logic?

Description

How can I improve the synthesis results of the clock wrapper clock enable logic?

Solution

If you are not using the Multiple Subsystem Generator block, you can improve the clock wrapper clock enable synthesis results by commenting out the "syn_keep" attribute attached to the clock enable signals.

This attribute would look like this in VHDL:

signal ce_1_sg_x0: std_logic;

attribute syn_keep: boolean;

attribute syn_keep of ce_1_sg_x0: signal is true;

signal ce_2_sg_x0: std_logic;

attribute syn_keep of ce_2_sg_x0: signal is true;

signal clkNet: std_logic;

After commenting out the syn_keep lines, the VHDL code would look as follows:

signal ce_1_sg_x0: std_logic;

attribute syn_keep: boolean;

-- attribute syn_keep of ce_1_sg_x0: signal is true;

signal ce_2_sg_x0: std_logic;

-- attribute syn_keep of ce_2_sg_x0: signal is true;

signal clkNet: std_logic;

When using Synplify or Synplify Pro, commenting out the "syn_keep" attribute has been seen to improve the routing by allowing Synplify to replicate the registers, and apply fan-out constraints to the clock enable logic.

AR# 23253
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article