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AR# 23267

8.2i MAP - What are latch-thrus in Virtex-5 designs?


Keywords: latch, thru, mrp, carry, MUX, .mrp

In the MAP report (.mrp) for Virtex-5 designs, the Design Summary contains information on latches and latch-thrus, as in the following example:

Slice Logic Utilization:
Number of Slice Registers: 6,859 out of 19,200 35%
Number used as Flip Flops: 6,819
Number used as Latches: 30
Number used as Latch-thrus: 10

What does the latch-thru count represent?


For any bit slice in a carry chain, contention for the general routing output MUX can occur for the MUXCY output, the XORCY output, or both. In this case, the register resource in the bit slice can be used as a logical pass-through latch gate. This use of the register resource alleviates the contention for the general routing output MUX by providing an alternate path to general routing for one of the contending signals. The most common occurrence of latch-thrus are at the end of a carry chain when both a sum and carry must exit a slice.

- Whenever a latch-thru is induced, no other flip-flops or latches can be packed into the same slice. This is the case because there is a single clock/gate signal in the slice, and it must be tied constant when a latch-thru is created, preventing any other latch or flip-flop from toggling.
- Whenever the two signals competing for the output MUX resource are the MUXCY and XORCY output signals, and a latch-thru can be induced, the XORCY output signal will utilize the latch-thru.
- A latch-thru cannot be induced for any signal that already appears on a comp output pin. One example is the MUXCY output of the D bit slice appearing on the COUT pin. The MUXCY output cannot be used to induce a latch-thru.
AR# 23267
Date 06/16/2006
Status Active
Type General Article