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  3. AR# 23292: 8.1.01.p01 System Generator for DSP - Why are the DSP48 Macro Reset and Clock Enable ports swapped?

AR# 23292

8.1.01.p01 System Generator for DSP - Why are the DSP48 Macro Reset and Clock Enable ports swapped?

Description

Why are the DSP48 Macro Reset and Clock Enable ports swapped?

Solution

This problem is due to a bug in the DSP48 Macro when global reset and enable are used together. 

 

This issue has been fixed in System Generator for DSP Path 8.1.01.p01 and later. See (Xilinx Answer 23293) for more information.

AR# 23292
Date 05/20/2014
Status Archive
Type General Article