This Answer contains the Release Notes for System Generator for DSP 8.1.01.p02.
Patch Installation Instructions
1. Before you install this patch, ensure that the following items are installed on your machine:
- ISE 8.1i Implementation tools and Service Pack 3 from Xilinx
- IP Update #1 for ISE 8.1i
- System Generator for DSP 8.1.01
- R14.1, R14.2, R14.3, or R2006a from MathWorks
2. Download the "sysgen8_1_01_p02.zip" file to a temporary directory (e.g., C:\Temp).
3. If you have any MATLAB sessions open, close them and restart MATLAB.
(Do not open any designs during the patch install.)
4. In the MATLAB command window, enter the following to start the installation process:
> cd C:\Temp
Follow any prompts from the GUI. The files are installed into your System Generator for DSP 8.1.01 for installation. The version information is updated to reflect the installation of the patch.
5. Restart MATLAB.
6. To check the version information, enter the following in the MATLAB command window:
Why are the DSP48 Macro Reset and Clock Enable ports swapped? See (Xilinx Answer 23292).
FIR Compiler reset does not work when using the FIR Compiler in single channel mode; why? See (Xilinx Answer 23354).
For System Generator for DSP 8.1.01 Known Issues, see (Xilinx Answer 23243).
This patch also contains all the fixes in System Generator for DSP 8.1.01.p01, see (Xilinx Answer 23293).
For System Generator for DSP release notes from other release versions, see (Xilinx Answer 29595).