Map prints out the following three errors, each related to the same problem (your signal names will vary):
<OUTPUT> Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Processing global clock buffers... ERROR:x4kma:148 - IBUF symbol `$1I89' (output signal=RESET_NET) cannot be merged into I/O "RESET". The two symbols have incompatible site types (e.g, one may be a flip-flop and the other a LUT). ERROR:x4kma:175 - IBUF symbol `$1I89' (output signal=RESET_NET) cannot be placed into IOB "RESET". You may be attempting to put more resources into this IOB than it can support. Please see the Xilinx Programmable Logic Data Book for information on the IOB structure of the target device. ERROR:x4kma:157 - OBUF symbol `$1I56' (output signal=Q_PAD8) cannot be combined into I/O "Q_PAD8". The two symbols have incompatible site types (e.g, one may be a flip-flop and the other a LUT).. </OUTPUT>
What has happened is that Map has expanded the "*" wildcard in the following placement constraint to include both IOBs as well as CLBs in the set of elements constrained by the statement,
place instance *:[clb_r2c1 clb_r10c3]
and tries to map both CLB and IOB components into the specified area.
Map does not recognize that the PLACE INSTANCE constraints in the example are intrinsically CLB-specific constraints.
The only workaround is to narrow down the set of instances referenced by the constraint to nets or blocks associated only with CLBs. It may be possible to do this by using part of an appropriate shared name string with the "*" wildcard symbol.
The alternative is to specify the constraints on a per-CLB basis.
Bug Reference #: 17298 R_Stm, KL
In the case of CLB constraints applied to hierarchys, the work around is to remove all I/O from the hierarchy and place it at the top level.