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AR# 23392

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Core - Updated Clocking scheme for Virtex-4 FPGA using internal clock dividers and 250 MHz reference clock

Description


There are two updates to the Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Core clocking scheme for Virtex-4 FPGA:
  • Virtex-4 FX GT11 jitter errata exceeds the IEEE Std 802.3-2002 specification when using a reference clock of 125 MHz. To improve the jitter performance of the transmitted serial line, a 250 MHz reference clock is recommended. For more information, see the Virtex-4 FX errata.
  • Virtex-4 CES2/3 requires an external clock divider for TXUSERCLK and RXUSERCLK. For CES4, the internal GT11 dividers can be used.

Note that since there is no longer a 31.25 MHz clock source present, the DCLK of the GT11 and Cal Block v1.4.1 must now be provided by alternative means. This must be between 25 Mhz and 50 Mhz, see (Xilinx Answer 23319).

Solution


This updated clocking scheme is available in the CES4 patch update. To download, see (Xilinx Answer 22327).
Following is a diagram of the updated clocking scheme for CES4 with the 250 MHz reference clock and internal clock divider:


Updated Clocking Scheme for CES4
Updated Clocking Scheme for CES4



To switch between reference clock frequencies of 250 MHz and 125 MHz:
250 MHz:

TXOUTDIV2SEL = 4
TXPLLNDIVSEL = 10
RXOUTDIV2SEL = 1
RXPLLNDIVSEL = 20


125 MHz:

TXOUTDIV2SEL = 4
TXPLLNDIVSEL = 20
RXOUTDIV2SEL = 1
RXPLLNDIVSEL = 40


To switch between internal clock dividers or to drive TXUSRCLK and RXUSRCLK from fabric sources:

Internal Dividers:

TX_CLOCK_DIVIDER = 10
RX_CLOCK_DIVIDER = 10


To provide TXUSRCLK and RXUSRCLK from fabric:

TX_CLOCK_DIVIDER = 00
RX_CLOCK_DIVIDER = 00
AR# 23392
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII