This Release Note is for the SPI-4.2 (POS-PHY L4) Lite Core v4.1 released in 8.2i IP Update 1 and contains the following:
- New Features
- Bug Fixes
- Known Issues
For the installation instructions and design tool requirements for 8.2i IP Update 1, see (Xilinx Answer 23479).
New Features in v4.1
Supports ISE 8.2i
Supports new signal pin SrcStatFrameErr to flag incorrect frame word received on TStat
Bug Fixes in v4.1
CR 221524: ERROR: sim:158 - Tcl error detected while configuring symbol pins. Corrected by disabling symbol (asy) file generation
CR 215699: Spartan 3E demonstration testbench runs the core at an inappropriate clock rate
CR 206779: "Fatal: (vsim-3421) Value 512 is out of range 0 to 511" error seen with demonstration testbench. Demonstration testbench fails to load in simulator when length of calendar sequence exceeds 510
(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?
(Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?
Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration.
Known Issues in v4.1
Constraints and Implementation Issues
(Xilinx Answer 22009)) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear.
(Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear.
(Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through BitGen, several "WARNING" messages appear.
(Xilinx Answer 22011) There are missing example constraints in the UCF file.
(Xilinx Answer 22012) TSClk unrouted for 3 regional clocks causing unrouted net error in PAR.
(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported."
General Simulation Issues
(Xilinx Answer 21319) TDat Error: Data mismatch error in timing simulation
(Xilinx Answer 21974) Timing simulation results in RStat Error : DIP2 error received. Expecting 01, received 00. SnkDip2ErrReqFlag = 0
(Xilinx Answer 21975) When simulating, the design example testbench will report that DataMaxT was violated.
(Xilinx Answer 22001) Design example results in warnings for source segmenting packets.
(Xilinx Answer 21350) Demo testbench results in RDat Protocal violation warnings.
(Xilinx Answer 21322) Timing simulation errors: SETUP, HOLD, RECOVERY violations
(Xilinx Answer 22026) Simulating SPI-4.2 Lite design results in "Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;"
(Xilinx Answer 20796) When targeting Virtex-4 design with SPI4.2, be advised of silicon issue.
(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.
SPI- 4.2 (PL4) Lite v3.1 KNOWN ISSUES
- The SPI-4.2 Lite v3.1 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 Lite v3.1 issues, see (Xilinx Answer 22390).