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AR# 23509

LogiCORE IP VLYNQ - Release Notes and Known Issues


This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE VLYNQ Bus Interface.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

You can access the VLYNQ Lounge at:


The VLYNQ core has been discontinued. Please see the Following PDN:



General LogiCORE VLYNQ Issues

(Xilinx Answer 31696) How do I know if my VLYNQ Core has initialized properly?


- Initial Release in ISE 11.1

New Features

- ISE 11.1 software support

Bug Fixes

- N/A

Known Issues

(Xilinx Answer 31694) Why does the CMDFIFO_FREE output freeze at 0x07 when the OPB Slave Outbound Command FIFO buffer is full?
(Xilinx Answer 33787) LogiCORE VLYNQ v1.4 - Is the CORDIC Core available for Spartan-6 and Virtex-6 FPGAs?


- Initial Release in ISE 10.1

New Features

- Support for device families Spartan-3A DSP and Virtex-5 FPGAs

Bug Fixes

- Core always times out irrespective of the type of license used - User's core times out even with a FULL license.

--- CR 450984/451159

- Core does not work when OPB_LENGTH is set to 1021, 1022 or 1023.

--- CR 454834

- Data sheet Inconsistencies

--- CR 437703, 437704, 430047, 450983

Known Issues

(Xilinx Answer 31694) Why does the CMDFIFO_FREE output freeze at 0x07 when the OPB Slave Outbound Command FIFO buffer is full?
(Xilinx Answer 31699) Why does the OPB interface lock up if there are long delays between data transfers when transferring 64-byte blocks?


- Initial Release in ISE 8.2i IP Update 2

New Features

- Support for Spartan-3A family devices.

Bug Fixes

- CR 234366: Updated UCF, example design and testbench files to resolve failing timing simulations.

- CR 423706: Bug fix for block memory reads.

Known Issues

(Xilinx Answer 29528) Why does the VLYNQ interface lock up after about four hours of operation?
(Xilinx Answer 24047) Why does the OPB clock fail to restart after it has been stopped?


- Initial Release in ISE 8.2i IP Update 1

New Features

- First release.

Bug Fixes

- N/A.

Known Issues

(Xilinx Answer 23764) Why does my VLYNQ Core fail to meet timing and my READ data not match my transmitted data?
(Xilinx Answer 29527) Why do I see corrupted data reads when using the VLYNQ Core?
AR# 23509
Date 11/10/2015
Status Active
Type Release Notes
  • VLYNQ Interface for Texas Instruments Processors
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