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AR# 23534

8.1i NGDBuild CPLDFit: FDCPE - Clock Enable logic is incorrectly removed

Description

Logic attached to the CE port of a Flip-Flop is incorrectly trimmed by the CPLDFit tools. This affects only the 9500 family, and not the 9500XL or XV or CoolRunner families.

Solution

This problem has been fixed in the latest 8.2i Service Pack available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.2i Service Pack 2.

If you wish not to install the service pack, you can work around this issue by gating the enable logic with the data input port. This will not result in any additional logic being used by the device.

Original:

my_ff : FDCPE port map (

Q => myff_out,

C => clk,

CE => ce,

D => din,

PRE => preset,

CLR => clear );

)

Work-around:

myff : fdcpe port map (

Q => myff_out,

C => clk,

CE => ce,

D => datain,

PRE => preset,

CLR => clear );

datain <= ( (din and ce) or (myff_out and not(ce)) ;

AR# 23534
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article