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AR# 23539

8.1 AccelDSP Synthesis Tool - Why Do I Get Memory Collision Errors During Verify -gate_level?


Why does Verify -gate_level pass even when the error message "Memory Collision Error" is present?


The key to understanding if Verify -gate_level passes or not is dependent upon the comparison of expected results to the actual results during simulation. If a simulation passes, it is because all the expected outputs are present after simulation of the structural netlist. Therefore, we need to understand how it is that a "Memory Collision Error" message can be displayed, yet have no effect on the results of simulation. 


If your design contains a Dual-Port Memory as defined by the "SetDirective -memmap dp_sync_ram" command, the potential exists that the generated RTL behavior will read and write from the same address during the same clock-cycle. Since the block RAM do not support this capability, the RTL behavior generated by AccelDSP creates a "pass-through" circuit when the read address and the write address are the same value. The effect is that input data is passed to the output and the data coming from the block RAM is ignored. 


The simulation models of the block RAMs contain checks to determine if the read and write address are the same values. If they are, the message is displayed during simulation, regardless if the output port of the block RAM used or not. The reason the Verification passes is that the circuit is not using the data from the block RAM during the condition that results in the "Memory Collision" message being displayed.

AR# 23539
Date 05/20/2014
Status Archive
Type General Article
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