We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23608

8.2.02 System Generator for DSP - Why do I receive an error during the NGC netlist Build for Multiple Subsystem Generator if I one of the subsystems has the clockwrapper disabled?


This problem relates to a System Generator design that is organized as multiple subsystems, that is with a "multiple subsystem generator" block and underlying system generator blocks. If the options for the NGC netlist in any of the underlying system generator blocks are set to disable writing a clock wrapper, the following error occurs and the combined netlist is not produced: 


".. An error occurred while generating using the Multiple Subsystem Generator block."


Currently you must enable the clock wrapper for all subsystems when using the Multiple Subsystem Generator Block to generate your design. This issue has been addressed in the System Generator for DSP 9.1 Software.

AR# 23608
Date 05/20/2014
Status Archive
Type General Article
Page Bookmarked