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AR# 23642

8.2i Virtex-5 MAP - DRC error due to MAP absorbing registers in DSP48E and leaving CEA1,CEB1 tied to GND

Description

General Description: A problem has been identified where MAP sometimes introduces DRC errors in DSP48Es when absorbing registers.

Frequency: This only happens when MAP absorbs from the output P bus and the only pipeline register left is the second A/BREG stage (i.e. A/B/M/PREG are already 1).

ERROR:PhysDesignRules:1504 - Dangling pins on

block:<M0/Mmac_M/M0/Mmac_M>:<DSP48E_DSP48E>. When the DSP48E AREG attribute

is set to 2 the CEA1 and CEA2 input pins cannot be unconnected or tied GND.

ERROR:PhysDesignRules:1508 - Dangling pins on

block:<M0/Mmac_M/M0/Mmac_M>:<DSP48E_DSP48E>. When the DSP48E BREG attribute

is set to 2 the CEB1 and CEB2 input pins cannot be unconnected or tied GND.

Work Around: Set the envronment variable XIL_MAP_NO_DSP48E_AUTOREG to 1.

Solution

This problem has been fixed in the latest 8.2i Service Pack available at:

<http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp>
The first service pack containing the fix is 8.2i Service Pack 1.

AR# 23642
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article