Keywords, distributed, memory, RAM16, pack
Packing can cause incorrect connection of address lines for distributed RAM16s. The root cause is that the packer sometimes incorrectly allows different combinations of RAM16s to be packed in any of the eight slots in any combination.
The rules that need to be followed in this case that are being ignored are:
1. If any 2 RAM share a LUT complex, the D5 and D6 must be shared.
2. If the D5 and D6 are shared, then a RAM16 in any of the other sites that is not shared must use the O5 output.
There is a packing restriction that has not been considered and therefore not enforced with regards to RAM.
The work-arounds for this issue are:
1. With constraints, pull 2 other compatible RAM16s into the slice to share the LUT sites with the A6 and B6 RAMs.
2. Put BEL=B5LUT and BEL=A5LUT constraints on the two RAM in the SLICE that do not share a LUT site.
3. Exclude the RAM16s from sharing any sites via other constraints.
This issue is scheduled to be fixed in 8.2i Service Pack 2.