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AR# 23679

LogiCORE Fibre Channel v2.1 Core - Updated clocking schemes for Virtex-4 FX CES4

Description

The v2.1 rev1 update to the Fibre Channel LogiCORE contains an updated clocking scheme for Virtex-4 FX devices for the CES4 silicon.

Solution

The changes to the clocking in the wrapper files are described in reference to figures 7-7 to 7-11 in the v2.1 User Guide 136: 

 

1 Gbps-only Virtex-4 Fibre Channel Core Clocking Scheme (Figure7-7) 

1- Remove the Speed Control block. Replacing with a wire from the DCLK BUFG to the Cal Block. 

2- Remove the RXRECCLK connection to the Cal Block from the GT11. 

3- Remove the CLKDV output from the DCM (TXUSRCLK now driven internally in the GT11) 

4- Remove the connection from the TXOUTCLK BUFG to the Cal Block. 

 

2 Gbps-only and 4 Gbps-only Virtex-4 Fibre Channel Core Clocking Scheme (Figures 7-8 and 7-9) 

1- Remove the Speed Control block. Replacing with a wire from the DCLK BUFG to the Cal Block. 

2- Remove the RXRECCLK connection to the Cal Block from the GT11. 

3- Remove the connection from the TXOUTCLK BUFG to the Cal Block. 

4- Remove the connection from the CLKDV BUFG to the TXUSRCLK input on the GT11 (now driven internally in the GT11). The CLKDV output is still used by the core. 

 

Multi-speed 1/2 Gbps and Multi-speed 2/4 Gbps Virtex-4 Fibre Channel Core Clocking Scheme (Figures 7-10 and 7-11) 

1- Remove the RXRECCLK connection to the Cal Block from the GT11. 

2- Remove the connection from the TXOUTCLK BUFG to the cal block. 

3- Remove the DCM on the TXOUTCLK BUFG. TXUSRCLK is no longer driven.

AR# 23679
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article