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AR# 23683

LogiCORE SPI-4.2 (POS-PHY L4) v8.1 - PAR - "ERROR:Place:832 - Delay element x should have a site assigned to it by now"

Description

When implementing Virtex-4 Core with Sink IDELAY insertion with global clocking ("Insert IDELAY on RDClk" option selected), I receive the following error when running PAR:

Phase 1.1

Phase 1.1 (Checksum:9ac830) REAL time: 45 secs

Phase 2.7

Phase 2.7 (Checksum:1312cfe) REAL time: 46 secs

Phase 3.31

Phase 3.31 (Checksum:1c9c37d) REAL time: 46 secs

Phase 4.2

....................................

ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR0/SLAVE should have a site assigned to it

by now.

ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR0/MASTER should have a site assigned to

it by now.

ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR1/SLAVE should have a site assigned to it

by now.

Solution

This is a design tool issue which has been fixed in ISE 8.2i Service Pack 2.

AR# 23683
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article