When implementing Virtex-4 Core with Sink IDELAY insertion with global clocking ("Insert IDELAY on RDClk" option selected), I receive the following error when running PAR:
Phase 1.1 (Checksum:9ac830) REAL time: 45 secs
Phase 2.7 (Checksum:1312cfe) REAL time: 46 secs
Phase 3.31 (Checksum:1c9c37d) REAL time: 46 secs
ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR0/SLAVE should have a site assigned to it
ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR0/MASTER should have a site assigned to
it by now.
ERROR:Place:832 - Delay element core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR1/SLAVE should have a site assigned to it
This is a design tool issue which has been fixed in ISE 8.2i Service Pack 2.