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AR# 23774

8.2 System Generator for DSP - Release Notes/README and Known Issues List


This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 8.2.

*URGENT - You must download the patch in (Xilinx Answer 24038) when installing ISE 8.2i Service Pack 3.

Also see (Xilinx Answer 24030) for more information about how this affects System Generator for DSP.


For System Generator for DSP release notes from other release versions see (Xilinx Answer 29595).

Known Issues in System Generator for DSP 8.2

System Generator for DSP 8.2 is a minor update, and is highly recommended for all System Generator for DSP 8.1 and 8.1.01 users. Please read the documentation because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is located at:

PDF Version is accessible from:


Support Software Issues

1. What software do I need to install System Generator for DSP? See (Xilinx Answer 17966).

2. XST bus elaboration might cause interface changes. See (Xilinx Answer 18650).

3. Why is my old System Generator for DSP missing, or seems to have disappeared when running xlVersion after installing 8.1? See (Xilinx Answer 22756).

4. NOTE: The Hardware in the Loop Ethernet Co-Simulation System ACE file was updated in System Generator for DSP 8.1.01. You should rerun the CF card update utility to ensure that you have the latest version installed on your System ACE Compact Flash Card.

Xilinx Blockset Issues

1. Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled? See (Xilinx Answer 22709).

2. PicoBlaze compiler script fails when using long module names. See (Xilinx Answer 16924).

3. Why does XST "Error 1370 ..." occur when using Verilog as my target language with a DDS v4.0 or v5.0 in my design? See (Xilinx Answer 22713).

4. Simulation mismatched for the reloadable DA FIR when performing back-annotated simulation. See (Xilinx Answer 19505).

5. Why does my System Generator for DSP 6.3 or 7.1 design (which passed generics to the black box for port widths) fail in System Generator for DSP 8.1? See Xilinx (Answer 22715).

6. Why are my Gateway In blocks behaving differently between System Generator for DSP 7.1, 8.1 and 8.1.01? See (Xilinx Answer 23250).

7. Why do I see the following error "Internal Block Error: This block set an illegal type on its "gw_out_inport" port. The type setting was illegal because Unknown type"? See (Xilinx Answer 23252).

8. Why does my design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in my design, and my target path is more than 160 characters? See (Xilinx Answer 23614).

9. Why do designs with more than 256 characters in the path fail to synthesize in XST? See (Xilinx Answer 23811).

10. Why do I receive errors when trying to implement the FFT v1.0 with Synplify Pro? See (Xilinx Answer 23813).

11. Why do I receive an error when the "Specify explicit sample period" option is selected and the "Provide enable port" or "Provide synchronous reset port" are not selected, on my Direct Digital Synthesis (DDS) v5.0 block? See (Xilinx Answer 23814).

General Issues

1. The following error is reported during generation: "Undefined function or variable." See (Xilinx Answer 15190).

2. Generation fails when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623).

3. User Hardware Co-Sim files disappear when installing System Generator for DSP update. See (Xilinx Answer 18646).

4. JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).

5. How can I improve the synthesis results of the clock wrapper clock enable logic? See (Xilinx Answer 23253).

6. Why do designs with more than 256 characters in the path fail to synthesize in XST? See (Xilinx Answer 23811).

7. Why does System Generator for DSP hang, when generating my large Verilog design? See (Xilinx Answer 20962).

8. Why do I receive "Error evaluating 'OpenFcn' callback of Xilinx Block. Error using ==> xlOpenGui Could not parse XLM file when I try to open a SysGen block on a network installation, or after installing a new version? See (Xilinx Answer 23223).

AR# 23774
Date 12/15/2012
Status Active
Type General Article