We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23799

8.2i ISE - Error message occurs with Generate Formality Netlist for a Virtex-5 project: "ERROR:NetListWriters:437 - Unknown output netlist type"


Keywords: formality, equivalence, NetGen

When I run Generate Post-translate Formality Netlist on a Virtex-5 project, the following message occurs:

"Release 8.2i - netgen I.29
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

ERROR:NetListWriters:437 - Unknown output netlist type.
For equivalence checking netlist, the -ecn switch is required.
For simulation netlist, the -ofmt switch is required with either
verilog or vhdl argument.
For static timing analysis netlist, the -sta switch is required.

Use "netgen -h <netlist_type>" to display netlist-specific options.
Valid netlist_types are:

equivalence or ecn (display options for equivalence checking netlist)
simulation or sim (display options for simulation netlist)
static or sta (display options for static timing analysis netlist)

netgen extracts design data from the input file and generates netlist compatible
with supported equivalence checking, simulation or static timing analysis tools.

Process "" completed successfully"


The message is misleading. This message is generated because the Generate Post-translate Formality Netlist is not available for Virtex-5 devices. An improved message has been added to NetGen in ISE 8.2.02i indicating that the specified device family is not supported.

This problem has been fixed in the latest 8.2i Service Pack available at:
The first service pack containing the fix is 8.2i Service Pack 2.
AR# 23799
Date 04/16/2009
Status Archive
Type General Article