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AR# 23801

8.2i Virtex-5 MAP - Over-utilized slice logic fails with placement errors rather than with over-mapped errors


The Virtex-5 mapper always uses a timing-driven algorithm that includes placement algorithms. Rather than reporting slice utilization as in previous architectures, the mapper now reports LUT or FF pairs to provide more useful information on the packing density. Since this change, designs with over-utilized slice logic fail with a placement error rather than with a clear indication of the over-utilization: 


"ERROR:Place:543 - Due to placement constraints, the following 7 components 

cannot be placed. The relative offsets of the components are shown in 

brackets next to the component names.  

LUT PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(6) (0, 0) 

LUT PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(6) (0, 1) 

FF PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(6) (0, 2) 

LUT PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(7) (0, 3) 

LUT PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(7) (0, 4) 

FF PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(7) (0, 5) 

FF PORTINF_AP_CORE/ATSAA/U_ATS2ATS/sr_atsc_state(8) (0, 8)" 


The MAP Report (.mrp) does contain some information that indicates the over-utilization, but this information is not indicated as the source of the failure: 


"Slice Logic Distribution: 

Either LUT or Flip-Flop pair used: 85,267 out of 69,120 123% 

Both LUT and Flip-Flop pair used: 24,832 out of 69,120 35%:


This issue is under investigation for improved error handling in ISE 9.1i.

AR# 23801
Date 05/20/2014
Status Archive
Type General Article
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