This Release Note is for the SPI-4.2 (POS-PHY L4) v8.2 Core released in 8.2i IP Update 2; it contains the following information:
- New Features
- Bug Fixes
- General Information
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 23831).
New Features in v8.2
- Supports Virtex-5 up to 1 Gbps in -1 speed grade
- Extended operating duration of the Full System Hardware Evaluation Core by 4x
- Sink core: low latency mode added for reading available data
- Sink core: Dynamic Phase Alignment (DPA) clock adjustment for Virtex-5
- Supports suspending Continuous DPA operation
- Enhanced DPA Diagnostic ports
- Dedicated IDELAYCTRL reset signal added
- Source core: maximum unsegmented packet size increased to 16 kbytes (SrcBurstLen)
Bug Fixes in v8.2
- CR 205723: GUI illegally allowed DataMaxT values between 1 to 15, which are not supported. This range of numbers of SPI-4.2 bus cycles between periodic training patterns will not be supported going forward. Currently, the GUI does not allow you to generate cores with DataMaxT set to these ranges.
- CR 235061: NGDBuild fails when DIFF_TERM constraints are applied to the RDat_P/N and RCtl_P/N inputs in a static alignment core configuration. Updated the DIFF_TERM constraints delivered in the example UCF for both static and dynamic alignment cores.
- Version 8.2 of the SPI-4.2 Core supports Virtex-4 and Virtex-5 family. For Virtex-II and Virtex-II Pro designs, use the latest version of the v6.x series of the SPI-4.2 Core.
- Version 8.2 Core is compatible with ISE 8.2i Service Pack 3.
- If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.
(Xilinx Answer 24014) Migrating SPI4.2 design from v8.1 to v8.2
(Xilinx Answer 23668) Migrating SPI4.2 design from v6.3 to v8.1
(Xilinx Answer 21386) When do I use Global Clocking vs Regional Clocking?
(Xilinx Answer 21069) When using Dynamic Phase Alignment or the SPI Core, RDClk must be running at least 220 MHz minimum
(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Core?
(Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
(Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?
(Xilinx Answer 21959) When I simulate an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported
(Xilinx Answer 22392) When using a Source Core with Slave Clocking, use clocks from another Master Source core, and not the general-purpose clock from the Sink core
Known Issues in v8.2
GUI and Core Generation Issues
(Xilinx Answer 23771) When generating the core, GUI allows illegal clocking options
Constraints and Implementation Issues
(Xilinx Answer 20000) When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear
(Xilinx Answer 21439) When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear
(Xilinx Answer 21320) When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear.
(Xilinx Answer 21363) PAR has problems placing components or completely routing the SPI4.2 design in my design
(Xilinx Answer 20280) Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O
(Xilinx Answer 20040) Timing Analyzer (TRCE) reports "0 items analyzed"
(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported."
(Xilinx Answer 20319) When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild
(Xilinx Answer 20017) The SPI-4.2 Core signals default to LVDS without the internal device termination. If internal termination is needed, it must be defined in the UCF. For a complete list of supported I/O, see (Xilinx Answer 20017)
General Simulation Issues
(Xilinx Answer 24027) Compiling XilinxCoreLib gives error : Error-[URMI] Instances with unresolved modules remain in the design.
(Xilinx Answer 24025) NetGen option "-pcf " is needed to generate SDF file for timing simulation
(Xilinx Answer 24026) When running simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest
(Xilinx Answer 21409) When using Dynamic Phase Alignment, the PhaseAlignComplete signal is not asserted and SnkOof is never de-asserted
(Xilinx Answer 21319) When running timing simulation on an SPI4.2 Design Example, several "TDat Error: Data Mismatch" messages are reported
(Xilinx Answer 21321) When running timing simulation on an SPI4.2 design with a Sink core set to Dynamic Alignment mode, several "Error: */X_ISERDES SETUP Low - - VIOLATION ON D WITH RESPECT TO CLK" messages are reported
(Xilinx Answer 21322) When running timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur
(Xilinx Answer 21362) When running Verilog timing simulation, TDat output is always "0000" and no training pattern is sent after reset
(Xilinx Answer 20030) When simulating an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation
(Xilinx Answer 15578) When simulating an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur
(Xilinx Answer 21316) When running timing simulation using the design example, DIP2 mismatch errors occur in the simulator
(Xilinx Answer 21959) When simulating an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported
(Xilinx Answer 20796) When targeting a Virtex-4 design with the SPI4.2 Core, a silicon issue exists.
(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.
- When I open the SPI4.2 GUI in CORE Generator using the hardware timeout evaluation license, it displays a pop-up message. The message indicates that the hardware timeout lasts for 6-8 hours. However, the core runs only two hours.
SPI- 4.2 (PL4) v8.1 KNOWN ISSUES
- The SPI-4.2 v8.1 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v8.1 issues, see (Xilinx Answer 23487).
SPI- 4.2 (PL4) v7.4 KNOWN ISSUES
- The SPI-4.2 v7.4 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.4 issues, see (Xilinx Answer 22300).
SPI- 4.2 (PL4) v7.3 KNOWN ISSUES
- The SPI-4.2 v7.3 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.3 issues, see (Xilinx Answer 21918).
SPI- 4.2 (PL4) v7.2 KNOWN ISSUES
- The SPI-4.2 v7.2 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.2 issues, see (Xilinx Answer 21032).
SPI- 4.2 (PL4) v7.1 KNOWN ISSUES
- The SPI-4.2 v7.1 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.1 issues, see (Xilinx Answer 20274).