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AR# 23849

LogiCORE Block Memory Generator v2.2 - Release Notes and Known Issues for 8.2i IP Update 2 (8.2i_Ip2)


Keywords: CORE Generator, ip2_im, mem, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, SDF

This Release Note is for the Block Memory Generator Core v2.2 released in 8.2i IP Update 2, and contains the following information:
- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 23831).

The Xilinx Block Memory Generator v2.2 LogiCORE should be used in all new Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-II/-E, Spartan-3E, and Spartan-3 designs wherever block memory is required. This core supersedes the Single Port Block Memory v6.2 and Dual Port Block Memory v6.3 cores, but is not a direct drop-in replacement. See the Block Memory Core Migration Kit available at:


New Features in v2.2

- Added support for Spartan-3A, Spartan-3 XA, Spartan-3E XA, and Virtex-4 XA
- Minimum depth has been reduced from eight to two
- Added support for Simple Dual Port block RAM primitives in Virtex-5

Bug Fixes in v2.2

CR 232997: Virtex-5 timing simulation failed with SDF file error: " # ** Error: (vsim-SDF-3261) ../../implement/results/routed.sdf(1200): Failed to find matching module path."

This is a NetGen SDF file generator issue and is fixed in ISE 8.2i Service Pack 1.

CR: 232994: The Verilog NetGen-generated model failed consistently for Virtex-5, producing incorrect outputs from the RAMB36 primitive on the DOUT during simulation.

This is a UniSim model issue and is fixed in 8.2i Service Pack1.

(Xilinx Answer 23686) Virtex-4, in structural (UniSim) simulation DOUTA changes on the wrong clock.
(Xilinx Answer 22699) Behavioral models did not flag collision for asymmetric read-write ports. Block Memory Generator v2.2 now flags collision for asymmetric read-write ports.
(Xilinx Answer 23682) Data sheet lacked the information on differences between older memory cores and the new Block Memory Generator when using one port as Read-Only.

Known Issues in v2.2

(Xilinx Answer 24104) When using Byte Write Enable feature, the data read-out from the memory might not match what is expected.
(Xilinx Answer 24061) Unexpected data is seen on the output as the memory is generated with the incorrect write mode.
(Xilinx Answer 24069) Memory is not initialized correctly using COE or "Filling Memory Locations" option.
(Xilinx Answer 24057) Spartan-3A is a supported device, although the table on page one of the data sheet "Supported Device Family" does not mention that this device is supported.
(Xilinx Answer 24033) Block Memory Resource Estimate (on last page of GUI) reports "undefined" .
(Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX".
(Xilinx Answer 23744) Invalid address input can cause the core to generate X's on the DOUT bus.
(Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate.

Device Issues

Please be aware of the Virtex-5 Errata posted on:

Block Memory Generator Core is subject to all block RAM issues listed in the Errata.
AR# 23849
Date 10/13/2006
Status Active
Type General Article